september 1995 47/69 st72e94 ST72T94 8-bit hcmos mcu with 6k eprom, eeprom and 16-bit timer with input capture and output compare 3.0 to 5.5v supply operating range 4mhz maximum clock frequency fully static operation -40 to +85 c operating temperature range run, wait, stop and ram retention modes user eprom: 6,144 bytes data ram: 224 bytes eeprom: 256 bytes 28 pin dual-in-line and so plastic packages for ST72T94 otp version 28 pin ceramic dual-in-line package for st72e94 eprom version 22 bidirectional i/o lines 6 interrupt wake-up programmable input lines 16-bit timer with input capture and dual output compare 2v ram data retention mode master reset and power-on reset compatible with st7294 (6k) and st7293 (3.25k) rom devices 8-bit data manipulation 63 basic instructions 17 main addressing modes 8x8 unsigned multiply instruction true bit manipulation complete development support on pc/dos real-time emulator full software package (cross-assembler, debugger) figure 1. pin description note 1. this pin is also the v pp input for eprom based devices pdip28 pso28 cdip28w (see end of datasheet for ordering information) int reset oscin oscout pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc5 v pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0 (icap) pc1 (ocmp1) pc2 pc3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vr0a1734 dd v ss pc4 (1)
48/69 st72e94 - ST72T94 1 general description 1.1 introduction the st72e94 and ST72T94 (following mentioned as st72e94) are eprom members with eep- rom of the st72 family of microcontrollers, in windowed ceramic (e) and plastic otp (t) pack- ages respectively, completely developed and pro- duced by sgs-thomson microelectronics using a n-well proprietary hcmos process. the eprom parts are fully compatible with their rom versions and this datasheet will thus provide only information specific to the eprom based devices. the reader is asked to refer to the datasheet of the st7294 and st7293 rom-based devices for further de- tails . the st72e94 is an user-programmable and eras- able device. it is best suited for development. the ST72T94 is a one-time programmable device (otp). it offers the best cost/flexibility trade-off for prototyping and preseries as well as most low to medium volume applications. the st72e94 and ST72T94 are hcmos micro- controllers from the st72 family. they are based around an 8-bit core industry standard and offers an enhanced instruction set. the processor runs with an external clock at 4 mhz with a 5v supply and 2mhz with a 3v supply. due to the fully static design of this device, operation down to dc is possible. under software control the st72e94 and ST72T94 can be placed in wait or halt mode thus reducing power consumption. the en- hanced instruction set and addressing modes af- ford real programming potential. in addition to standard 8 bit data management the st72e94 and ST72T94 feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. the devices include an on-chip oscillator, cpu, eprom, ram, eeprom, i/o, and one tim- er with 1 input capture and 2 output compare sys- tems. figure 2. st72e94 block diagram note 1. eprom version only control port a port b port c timer system ram 224 bytes rom or eprom (1) 6144 kbytes pcl pch sp x y a cc address bus data bus pa0 - pa7 (8-bit) pb0 - pb7 (8-bit) pc0 - pc5 (6-bit) v dd v ss oscin oscout int/v pp (1) reset oscillator power supply 8 -bit core alu vr01735e internal clock watchdog eeprom 256 bytes comp1 (pc1) icap (pc0)
49/69 st72e94 - ST72T94 1.2 pin description v dd . power supply. v ss . ground. oscin, oscout. oscillator input and output pins. these pins are to be connected to a parallel reso- nant crystal or ceramic resonator. an external clock source can also be input through oscin. reset. the active low input signal forces the ini- tialisation of the mcu. this event is the first priori- ty interrupt. this pin is switched output low when the watchdog has released. it could be used to re- set external peripherals. int/v pp . is the external interrupt signal. software configuration allows four triggering modes. in the eprom programming mode, this pin acts as the programming voltage input v pp . icap (pc0). input capture signal going to the tim- er system. this signal, according to a mask op- tion, can be an icap pin or pc0 pin. when pc0 is defined as icap, the internal pull-up resistor is not connected. ocmp1 (pc1). output compare signal coming from the timer system. this output signal, ac- cording to a mask option, can be an ocmp1 pin (for output compare 1 of the timer) or pc1 pin. when pc1 is defined as ocmp1, the internal pull- up resistor is not connected. pa0-pa7, pb0-pb7, pc0-pc5. these 22 lines are standard i/o lines, programmable as either in- put or output. port a. 8 standard i/o lines, bit programma- ble, accessed through ddra and dra regis- ters. according to a mask option, the outputs can be defined as a standard push-pull output port or as an open drain output port. according to anoth- er mask option, a pull-up resistor can be added on each line when it is defined as an input. port b. 8 standard i/o lines bit programmable accessed through ddrb and drb registers. according to another mask option, a pull-up re- sistor can be added on each line when it is de- fined as an input. port c. 6 standard i/o lines accessed through ddrc and drc registers. according to a mask option, these 6 lines can become 6 falling edge sensitive interrupt lines all linked to a single inter- rupt vector or 6 standard input ports tied to v dd through an internal pull-up resistor. these nega- tive edge sensitive interrupt lines can wake-up the st72e94 from wait or halt mode. this feature allows to build low power applications when the st72e94 can be waken-up from key- board push.
50/69 st72e94 - ST72T94 pin description (continued) table 1. st72e94 pin configuration name function description pin assignment int/v pp i interrupt / eprom programming voltage 1 reset i/o reset 2 oscin i oscillator 3 oscout o oscillator 4 pb7 i/o standard port (bit programmable) 5 pb6 i/o standard port (bit programmable) 6 pb5 i/o standard port (bit programmable) 7 pb4 i/o standard port (bit programmable) 8 pb3 i/o standard port (bit programmable) 9 pb2 i/o standard port (bit programmable) 10 pb1 i/o standard port (bit programmable) 11 pb0 i/o standard port (bit programmable) 12 pc5 i/o standard port (falling edge interrupt line) 13 pc4 i/o standard port (falling edge interrupt line) 14 pc3 i/o standard port (falling edge interrupt line) 15 pc2 i/o standard port (falling edge interrupt line) 16 pc1 (ocmp1) i/o standard port (falling edge interrupt line or timer output compare) 17 pc0 (icap) i/o standard port (falling edge interrupt line or timer input capture) 18 pa7 i/o standard port (bit programmable) 19 pa6 i/o standard port (bit programmable) 20 pa5 i/o standard port (bit programmable) 21 pa4 i/o standard port (bit programmable) 22 pa3 i/o standard port (bit programmable) 23 pa2 i/o standard port (bit programmable) 24 pa1 i/o standard port (bit programmable) 25 pa0 i/o standard port (bit programmable) 26 v dd i/o power supply 27 v ss i/o ground 28
51/69 st72e94 - ST72T94 1.3 memory map as shown in figure 3, the mcu is capable of ad- dressing 8192 bytes of memory and i/o registers. in the st72e94, 7696 of these bytes are user ac- cessible. note: in the st7293 only 3.25k bytes are user accessi- ble. this should be taken into account by the user when programming the st72e94 to emulate the st7293 . the locations consist of 32 bytes of i/o registers (only 20 are used), 224 bytes of ram, 256 bytes of eeprom and 6kbytes of user rom. the ram space includes 64 bytes for the stack from 0ffh to 0c0h. programs that only use a small part of the allocated stack locations for interrupts and/or sub- routine stacking purpose can use the remaining bytes as standard ram locations. the highest address bytes contains the user de- fined reset and interrupt vectors. figure 3. memory map i/o and registers 32 bytes ram 224 bytes (stack) 64 bytes 256 bytes reserved 1280 bytes reserved 240 bytes port c wake-up (high byte) port a data register port b data register port c data register/interrupts port a data direction register port b data direction register port c data direction register eeprom control register miscellaneous register timer control register timer status register capture high register 1 capture low register 1 counter high register compare low register 1 compare high register 1 counter low register alternate counter high register alternate counter low register compare high register 2 ports 6 bytes eeprom/cbulk control 1 byte miscellaneus 1 byte timer 12 bytes 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh compare low register 2 1fh 0000 0031 0032 0191 0192 0255 0256 0512 0511 1791 1792 7935 7936 8175 8176 0000h 1fffh 1ff0h 1fefh 1f00h 1effh 0700h 06ffh 01ffh 0200h 00ffh 00c0h 00bfh vr01847c eeprom reserved reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 1fffh 1ff4h 1ff5h 1ff6h 1ff7h 1ff8h 1ff9h 1ffah 1ffbh 1ffch 1ffdh 1ffeh 0100h port c wake-up (low byte) timer overflow (high byte) timer overflow (low byte) timer output compares (high byte) timer output compares (low byte) timer input capture (high byte) timer input capture (low byte) external interrupt (int) (high) external interrupt (int) (low) trap instruction (high byte) trap instruction (low byte) reset and power on (por) (high) reset and power on (por) (low) user vectors 16 bytes 8191 1ff0h 1ff1h 001fh 0020h 1ff3h not used 1ff2h not used option byte (1) 0513 0201h (1) only on eprom/otp version 6k user rom or eprom 6144 bytes
52/69 st72e94 - ST72T94 1.4 option byte an additional mode is used to configure the part for programming of the eprom. this is set by a +12.5 voltage applied to the int/v pp . the eprom memory may be programmed by us- ing the eprom programming boards (epb) avail- able from sgs-thomson. the rom devices of the st72 family can be con- figured through mask options. in eprom devices, most mask options are replaced by eprom bits grouped in the option byte. the configuration of the device is made by programming the option byte. the option byte is not in the user memory space. the option byte is accessed only if the device is in programming mode and location 0200h is ad- dressed. the epb provides all the functionality to select and program the option byte. b7 = wiw : watchdog in wait. 1 : watchdog suspended during wait 0 : watchdog active during wait b6 = wdms : watchdog enable mode . 1 : watchdog in software select mode 0 : watchdog in auto-enable mode b5 = pbip : port b input pull-up. 1 : pull-up enabled or port b (when input) 0 : no pull-up on port b b4 = pcws : port c wake-up select. 1 : port c i/o functions enabled 0 : port c interrupt wake-up inputs enabled b3 = pc1s : pc1 select. 1 : timer ocmp1 connected to pin 17 0 : pc1 i/o function connected to pin 17 70 wiw wdms pbip pcws pc1s pc0s pa0s paip b2 = pc0s : pc0 select. 1 : timer icap connected to pin 18 0 : pc0 i/o function connected to pin 18 b1 = pa0s : port a output select . 1 : port a output is push-pull 0 : port a output is open-drain b0 = paip : port a input pull-up. 1 : pull-up enabled on port a (when input) 0 : no pull-up on port a 1.5 eprom erasure (st72e94 only) the st72e94 is erased by exposure to high inten- sity uv light through the transparent window. this exposure discharges the floating gate to its initial state through induced photo current. it is recommended that the st72e94 be kept out of direct sunlight because the uv content of sun- light can cause temporary functional failure. ex- tended exposure to room level fluorescent lighting will also cause erasure. an opaque coating (paint, tape, label, etc...) should be placed over the pack- age window if the product is to be operated under these lighting conditions. covering the window also reduces idd in stop mode due to photo diode currents. an ultraviolet source of wave length 2537 ? yield- ing a total integrated dosage of 15 watt-sec/cm is required to erase the st72e94. this device will be erased in 15 to 20 minutes if an uv lamp with a 12mw/cm power rating is placed 1 inch from the lamp without filters. 1.6 voltage range the st72e94 and ST72T94 operate with a mini- mum supply voltage of 3.0v when the st7294 op- erates from 2.5v.
53/69 st72e94 - ST72T94 2 electrical characteristics 2.1 absolute maximum ratings the st72e94/t94 devices contain circuitry to pro- tect the inputs against damage due to high static voltage or electric field. nevertheless it is advised to take normal precautions and to avoid applying to this high impedance voltage circuit any voltage higher than the maximum rated voltages. it is rec- ommended for proper operation that v in and v out be constraint to the range: v ss v in and v out v dd to enhance reliability of operation, it is recom- mended to configure unused i/os as inputs and to connect them to an appropriate logic voltage level such as v ss or v dd . all the voltage in the following tables are refer- enced to v ss . stresses above those listed as aabsolute maxi- mum ratingso may cause permanent damage to the device. functional operation of the device at these conditions is not implied. exposure to maxi- mum rating conditions for extended periods may affect device reliability. table 2. absolute maximum rating (voltage referenced to v ss ) symbol ratings value unit v dd supply voltage -0.3 to +6v v v in input voltage v ss -0.3 to v dd +0.3 v iv dd -iv ss total current into vss/vdd pins 50/20 ma i current drain per pin excluding v dd and v ss 20 ma t a operating temperature range t l to t h 0 to +70 c t stg storage temperature range -65 to +150 c
54/69 st72e94 - ST72T94 2.2 power considerations t j , the average chip-junction temperature in celsi- us can be calculated from the following equation: t j =t a +(p d x q j a ) (1) where: t a is the ambient temperature in c, q j a is the package thermal resistance, junction-to-ambient in c/w, p d the sum of p int and p i/o , p int equals i cc time v cc , watts-chip internal power p i/o the power dissipation on input and output pins, user determined. for most applications p i/o 55/69 st72e94 - ST72T94 2.3 dc electrical characteristics (t a = -40 c to +85 c unless otherwise specified) note 1. when option is chosen symbol test conditions min. typ. max. unit v ol v oh output voltage, iload 10.0 m a v dd -0.1 0.1 v v oh output high voltage i load =0.8ma, pa0-pa7,pb0-pb7,pc0-pc5 v dd -0.8 v v ol output low voltage i load =1.6 ma, pa0-pa7,pb0-pb7,pc0-pc5,reset 0.4 v v ih input high voltage pa0-pa7,pb0-pb7,pc0-pc5, int, reset 0.7xv dd v dd v v il input low voltage pa0-pa7,pb0-pb7,pc0-pc5, int, reset v ss 0.2xv dd v v rm data retention mode (0 to 70 c) 2 v i il i/o ports hi-z leakage current pa0-pa7,pb0-pb7, pc0-pc5 10 m a i in input current: reset, int, icap 1 m a c out capacitance: ports (as input or output) 12 pf c in reset, int, icap 8pf r pu port a, b, c (1) ,v dd = 3.5v, v in = 0v 125 250 500 k w
56/69 st72e94 - ST72T94 2.4 ac electrical characteristics (t a = -40 c to +85 c unless otherwise specified) notes: 1. run (operating) idd, wait i dd measured using external square wave clock all inputs 0.2v from rail, no dc load, less than 50pf on all outputs, ci = 20pf on oscout. 2. wait, halt all i/o configured as inputs, v il = 0.2v, v ih =v dd -0.2v. 3. halt, oscin = v ss . 2.5 control timing (t a = -40 c to +85 c unless otherwise specified) note 1. the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. symbol parameter test conditions value unit min. typ. max. v dd operating supply voltage run mode halt mode eeprom write eeprom read 3.0 2.0 3.0 3.0 5.5 v i dd supply current (1) (2) (3) run mode v dd =5v,f osc =4mhz v dd =3.0v,f osc =455khz wait mode v dd =5v,f osc =4mhz v dd =3.0v,f osc =455khz halt mode v dd =5v,t a =70 c 1.8 0.9 1 2.5 0.7 1.5 500 10 ma ma ma ma m a symbol parameter test condition s value unit min. typ. max. f osc frequency of operation v dd =5v v dd =3.0v dc dc 4 2 mhz t ilch halt mode recovery startup time crystal oscillator 50 ms t rl external reset input pulse width 1.5 t cyc t porl power reset output 4096 t cyc t dogl watchdog reset output pulse width 1.5 t dog watchdog time-out 6144 7168 t cyc t ilih interrupt pulse width int portc 125 125 ns t ilil interrupt pulse period (1) t cyc t oxov crystal oscillator startup time 50 ms t ddr supply rise time 10% to 90% 0.01 100 ms
57/69 st72e94 - ST72T94 2.6 eeprom symbol parameter test conditio ns value unit min. typ. max. t wee eeprom write time 0 to 70 c28ms endurance eeprom write/erase cycles q a lot acceptance criteria 300.000 > 1 million cycles retention eeprom data retention t a =55 c10 years
58/69 st72e94 - ST72T94 3 general information sgs-thomson offers st7 devices in eprom and otp as well as in the rom version. this range of product options provides the st7 user with maximum of flexibility for his application needs. the otp rather than the rom version of the st7 is recommended when the customer's quantity re- quirement is relatively small on a given code - e.g. less than 10 thousand pieces. but the otp solu- tion is also popular even for volumes when the customer has a need for reduced leadtime, wheth- er pre-production, an unforecasted increase in de- mand, or a quick program change. and the otp is often preferred by those customers who have sev- eral codes running concurrently since they need purchase and stock only one vendor sales type. however, it must be understood that the rom and otp follow different production flows and that the difference between these flows, in particular the method by which final electrical test is performed, may have an impact on the customer. the basic production flow is as follows: wafer diffusion electrical test of dice (wafer sort) assembly (encapsulation) final electrical test for rom parts, the customer program is included at a specific mask of the wafer. therefore, all of the product's functionality is present in both the die and the assembled product and this functionality can be fully evaluated at both wafer sort and final electrical test. sgs-thomson fully tests the rom version's functionality at both wafer sort and final test, thus ensuring conformance to the elec- trical specification and a low reject rate. but for otps there exists an additional feature that must be tested: programmability.the program memory of an otp should be seen as a collection of fuses that will be blown during programming. these fuses can be orecoveredo by lightening the die with uv light. this recovery is no longer possi- ble once the otp die has been encapsulated in an opaque plastic package. the programmability and data retention can only be fully tested at wafer sort. at this step the dice are electrically tested and the memory is programmed to verify programmability. then the wafers are placed in high temperature bake in order to provoke any possible memory re- tention defects. they are then retested to check data retention. after this test, uv light is used to orecovero the fuses and the good dice are assem- bled. although the programmability of the otp dice is verified as fully functional at probe test, the die en- capsulation process has the potential to affect this function in the finished product. it is therefore nec- essary that in addition to electrical final test, a pro- grammability test be made. however since uv light cannot be used to erase an otp's pro- grammed byte once the die has been encapsulat- ed it is then impossible to write a test pattern and thus to check 100% of the user program area. for this reason the final test is limited to a reserved number of bytes which are programmed and then verified. as the programmability of the otp cannot be fully tested once the die has been encapsulated, unlike the rom or eprom versions, a customer should find a programming reject rate below 1.0% and a data retention reject rate below 0.5% when pro- gramming is performed using qualified program- ming tools. apart from the programmability, the otp has the same reject as eprom and rom versions. in order to lower the reject levels for programma- bility and data retention, sgs-thomson is con- tinually pursuing technology improvements in are- as such as soft die handling, low stress com- pounds, and passivation layer enhancements.
59/69 st72e94 - ST72T94 3.1 package mechanical data figure 4. 28-ceramic dual in line package, 600-mil width 3.2 ordering information ordering information table sales types rom size temperature range package ST72T94c6b6 6k -40 c to +85 c pdip28 ST72T94c6m6 pso28 st72e94c6f0 25 c cdip28 dim . mm inches min typ max min typ max a 5.71 0.225 a1 0.50 1.78 0.020 0.070 b 0.40 0.55 0.016 0.022 b1 1.17 1.42 0.046 0.056 c 0.22 0.31 0.009 0.012 d 38.10 1.50 d1 1.52 2.49 0.060 0.098 e------ e1 13.05 13.36 0.514 0.526 l 3.00 0.118 e1 2.29 2.79 0.090 0.110 ? 6.86 7.36 0.270 0.290 number of pins n28
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